Characteristics of CMOS device isolation for the ULSI age

Scaling requirements for abrupt active-isolation transitions, isolation depth, and isolation planarity are discussed quantitatively. We review how LOCOS and STI isolation are being improved to meet these requirements. Independent of fabrication techniques, we see that a necessary consequence of achieving the desired narrow isolation and abrupt transitions is a discrete edge parasitic. We show that the edge parasitic can be distinguished from the planar channel and can be characterized separately. Edge device sensitivities are investigated with experiment and simulation to show that design and process control of the discrete edge parasitic will be a significant thrust of device engineering for future isolation technologies.<>