Low-power RF circuits for multi-standard WLAN transceivers

Circuit design techniques for integrating low-power multi-standard WLAN transceivers are presented in this paper. Several circuital approaches have been implemented and successfully demonstrated for the most critical blocks of a WLAN transceiver. The transmitter front-end is implemented by means of a current-reuse variable-gain up-converter. The circuit provides an output 1-dB compression point of 5.3 dBm, while consuming only 45 mA from a 3-V supply voltage. Moreover, a linear-in-dB gain control characteristic is achieved over a 35-dB dynamic range. In the receiver chain, a variable-gain LNA allows excellent noise figure and linearity performance to be achieved with low power consumption. The PLL makes use of a transformer-based VCO featuring low-phase noise and wide tuning range performance.