Low-temperature integrated process below 500/spl deg/C for thin Ta/sub 2/O/sub 5/ capacitor for giga-bit DRAMs

Author

Takaishi, Y. ; Sakao, M. ; Kamiyama, S. ; Suzuki, H. ; Watanabe, H.

Author_Institution

ULSI Device Dev. Lab., NEC Corp., Kanagawa, Japan

fYear

1994

fDate

11-14 Dec. 1994

Firstpage

839

Lastpage

842

Abstract

A new low-temperature integrated (LTI) process has been developed for giga-bit DRAMs with a thin Ta/sub 2/O/sub 5/ capacitor. The maximum process temperature after capacitor formation is restricted to lower than 500/spl deg/C in the LTI process. This process can reduce the capacitor leakage current by approximately four orders of magnitude in comparison with conventional high-temperature processes. A ten times improvement in data-retention time has been verified in an experimental DRAM device with 2.5 nm Ta/sub 2/O/sub 5/ capacitors by the LTI process.<>

Keywords

DRAM chips; capacitor storage; leakage currents; semiconductor device manufacture; tantalum compounds; thin film capacitors; 2.5 nm; 500 C; DRAM device; Ta/sub 2/O/sub 5/; capacitor formation; capacitor leakage current; data-retention time; giga-bit DRAMs; low-temperature integrated process; maximum process temperature; thin Ta/sub 2/O/sub 5/ capacitor; Annealing; Capacitors; Etching; Glass; Leakage current; Planarization; Plasma applications; Plasma temperature; Random access memory; Rapid thermal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1994. IEDM '94. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-2111-1

Type

conf

DOI

10.1109/IEDM.1994.383294

Filename

383294