On the cryogenic performance of ultra-low-loss, wideband SPDT RF switches designed in a 180 nm SOI-CMOS technology

Author

Cardoso, A.S. ; Chakraborty, P.S. ; Omprakash, A.P. ; Karaulac, N. ; Saha, P. ; Cressler, J.D.

Author_Institution

Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA

fYear

2014

fDate

6-9 Oct. 2014

Firstpage

1

Lastpage

2

Abstract

The RF cryogenic performance of ultra-low-loss, wideband (DC to 40 GHz) single-pole double-throw (SPDT) RF switches implemented in a 180 nm SOI CMOS technology is reported for the first time. Results show that the switch insertion loss (IL), isolation (ISO), small- and large-signal linearity all improve as the temperature decreases. DC characterization of individual transistors was performed and analyzed to provide insight into the mechanisms underlying the observed changes in the RF switches.

Keywords

CMOS integrated circuits; cryogenic electronics; field effect MMIC; low-power electronics; microwave switches; silicon-on-insulator; DC characterization; RF cryogenic performance; SOI CMOS technology; frequency 0 Hz to 40 GHz; isolation; large-signal linearity; size 180 nm; small-signal linearity; switch insertion loss; transistors; ultralow-loss wideband single-pole double-throw RF switches; Cryogenics; ISO; Linearity; Loss measurement; Radio frequency; Temperature sensors;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2014 IEEE

Conference_Location

Millbrae, CA

Type

conf

DOI

10.1109/S3S.2014.7028204

Filename

7028204