An evaluation methodology for the security of cryptosystems

This paper describes an integrated circuit design methodology which evaluates at the gate level the resistance of the circuit to a class of attacks, among them is the well-known Differential Power Analysis (DPA). This is of particular concern since it enables the designer to detect design strengths and weaknesses and to compare and choose different circuitpsilas architectures at an early stage of the design flow. The proposed methodology has been applied to different hardware models of the Advanced Encryption Standard (AES) and highlights substantial differences between the models in terms of area and security.