DfT and on-line test of high-performance data converters: a practical case

This paper addresses the practical implementation of a Design-for-Testability (DfT) technique applicable to digitally-corrected pipelined Analog-to-Digital Converters (ADC). The objective of this Dft is to improve both the on-and off-line testability of these important mixed-signal ICs. Because of the self-correction capability, such a kind of converters has some inherent insensitivity to the effect of faults which represents a disadvantage for testing and diagnosis. We will show that potentially malfunctioning units can be concurrently identified with low extra circuitry. In addition, this structure-based DfT scheme can also be useful to reduce the time in production-level testing. A CMOS switched-capacitor 10-b ADC is used as demonstrator of the proposed technique