A low power programmable FIR filter using sharing multiplication technique

A finite impulse response (FIR) programmable filter is implemented using computation sharing multiplication (CSHM) technique to reduce power consumption and improve performance. Both carry select adders (CSLA) and carry look-ahead adders (CLA) are used to determine power consumption, throughput and area of the proposed design. A 10-tap programmable FIR digital filter was implemented in CMOS 180 nm technology and a maximum clock frequency of 1.42 GHz was achieved. The area is determined to be 516 K transistors with latency of 131 clock cycles and power consumption of 2.966 W.