Single-ended disturb-free 5T loadless SRAM Cell using 90 nm CMOS process

Author

Chen, Sih-Yu ; Wang, Chua-Chin

Author_Institution

Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan

fYear

2012

fDate

May 30 2012-June 1 2012

Firstpage

1

Lastpage

4

Abstract

A novel single-ended load SRAM cell is proposed in this study, where a loadless SRAM cell with write assistant loop and an isolated wordline-controlled transistor (WLC) is revealed. A shared bitline inverter is included to boost the read access speed at the minimal expense of area cost. The energy dissipation per write/read operation is found to be 0.479/0.091 fJ provided that the SRAM cells is supplied a 0.6 V VDD region using a typical 90 nm CMOS technology. The proposed cell is proved to attain the smallest area, PDP (power-delay product) and disturb-free during the memory access.

Keywords

CMOS memory circuits; SRAM chips; CMOS process; PDP; WLC; bitline inverter; disturb-free 5T loadless SRAM cell; energy dissipation; power-delay product; size 90 nm; wordline-controlled transistor; write assistant loop; CMOS process; Inverters; Noise; Random access memory; Semiconductor device modeling; Timing; Transistors; disturb-free; loadless; power-delay product (PDP); single-ended SRAM cell; subthresold region;

fLanguage

English

Publisher

ieee

Conference_Titel

IC Design & Technology (ICICDT), 2012 IEEE International Conference on

Conference_Location

Austin, TX

ISSN

pending

Print_ISBN

978-1-4673-0146-6

Electronic_ISBN

pending

Type

conf

DOI

10.1109/ICICDT.2012.6232848

Filename

6232848