Rapid thermal annealing for H passivation of polysilicon MOSFETs from Si/sub 3/N/sub 4/ overcoat

Author

Batra, S. ; Park, K. ; Kyono, C. ; Bhattacharya, S. ; Banerjee, S. ; Maziar, C. ; Kwong, D. ; Tasch, A. ; Rodder, M. ; Sundaresan, R.

Author_Institution

Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA

fYear

1989

fDate

3-6 Dec. 1989

Firstpage

455

Lastpage

458

Abstract

It is shown that rapid thermal annealing is an effective technique for H passivation of the Si dangling bonds using Si/sub 3/N/sub 4/ as a solid source of H. Rapid thermal annealing (RTA) can yield passivated MOSFETs with an on/off ratio of 10/sup 7/ compared to 10/sup 6/ for passivation by furnace annealing. The subthreshold slope, threshold voltage, and channel transconductance also improve because passivation by RTA is more effective and, consequently, the grain boundary potential heights in the channel are smaller than after furnace passivation. A direct correlation between grain boundary potential barrier height, Hall mobility, and MOSFET behavior as a function of H passivation by both furnace annealing and RTA is obtained.<>

Keywords

Hall effect; elemental semiconductors; grain boundaries; incoherent light annealing; insulated gate field effect transistors; passivation; protective coatings; silicon; H passivation; Hall mobility; RTA; Si dangling bonds; Si/sub 3/N/sub 4/ overcoat; Si/sub 3/N/sub 4/-Si; channel transconductance; grain boundary potential heights; on/off ratio; passivated MOSFETs; polysilicon MOSFET; rapid thermal annealing; subthreshold slope; threshold voltage; Furnaces; Grain boundaries; MOSFETs; Passivation; Rapid thermal annealing; Silicon; Solids; Thin film transistors; Threshold voltage; Transconductance;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1989. IEDM '89. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-0817-4

Type

conf

DOI

10.1109/IEDM.1989.74320

Filename

74320