System-level optimization and benchmarking of graphene PN junction logic system based on empirical CPI model

Many novel devices are being pursued in recent years to augment or even replace CMOS technology. It is, therefore, important to develop a methodology to effectively evaluate the system-level performance of the emerging technologies. In this paper, an empirical cycles per instruction (CPI) model is presented based on Intel microprocessor family, which can be utilized to quantify the chip throughput for an emerging device technology at the early stage of technology development without detailed design and optimization of a full processor. Graphene pn junction devices are used as a platform for the proposed methodology. It is demonstrated that for the same power density and die size area, the maximum throughput of an optimized graphene logic single-core system can be 35% higher than that of its CMOS counterpart at 15nm technology node.