nFET FDSOI activated by low temperature solid phase epitaxial regrowth: Optimization guidelines

Author

Pasini, L. ; Batude, P. ; Casse, M. ; Brunet, L. ; Rivallin, P. ; Mathieu, B. ; Lacord, J. ; Martinie, S. ; Fenouillet-Beranger, C. ; Previtali, B. ; Rambal, N. ; Haond, M. ; Ghibaudo, G. ; Vinet, M.

Author_Institution

Leti, CEA, Grenoble, France

fYear

2014

fDate

6-9 Oct. 2014

Firstpage

1

Lastpage

2

Abstract

Low temperature (LT) activation on Fully Depleted Silicon On Insulator by SPER is needed for 3D sequential integration and also provides interest to obtain highly doped abrupt junctions in the standard planar technology. In this work, through the confrontation of electrical data and KMC process simulation we identify the efficient lever to optimize the low temperature device performance. This work evidences that the most suitable integration for LT FET implies a LDD implantation before the first spacer and the raised source drain epitaxy.

Keywords

cryogenic electronics; field effect transistors; silicon-on-insulator; solid phase epitaxial growth; 3D sequential integration; KMC process simulation; LDD implantation; LT activation; SPER; electrical data; first spacer; fully depleted silicon on insulator; highly doped abrupt junctions; low temperature device performance; low temperature solid phase epitaxial regrowth; nFET FDSOI; optimization guidelines; raised source drain epitaxy; standard planar technology; Epitaxial growth; Guidelines; Implants; Logic gates; Optimization; Performance evaluation;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2014 IEEE

Conference_Location

Millbrae, CA

Type

conf

DOI

10.1109/S3S.2014.7028214

Filename

7028214