Title :
Extracting gate-level networks from simulation tables
Author :
Wohl, Peter ; Waicukanski, J.
Author_Institution :
Synopsys Inc., Williston, VT, USA
Abstract :
Most library development effort is invested in coding and verifying custom or special function cells that cannot be easily represented by traditional gates such as AND, OR, and are naturally encoded as tables. The library reader described in this paper reads in existing simulation libraries and converts tables into efficient gate-level models for use by test-generation and other tools, thus automating the most engineering-intensive task of library development
Keywords :
circuit CAD; combinational switching; decision diagrams; integrated circuit design; logic CAD; C++ language; coding; gate-level networks; library development; models; simulation libraries; simulation tables; special function cells; test-generation; verifying; Application specific integrated circuits; Automatic testing; Circuit simulation; Circuit testing; Design automation; Formal verification; Hardware design languages; Libraries; Maintenance engineering; Microcontrollers;
Conference_Titel :
Test Conference, 1998. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-5093-6
DOI :
10.1109/TEST.1998.743206
