DocumentCode
252554
Title
A cross-layer design framework and comparative analysis of SRAM cells and cache memories using 7nm FinFET devices
Author
Shafaei, A. ; Shuang Chen ; Yanzhi Wang ; Pedram, M.
Author_Institution
Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
fYear
2014
fDate
6-9 Oct. 2014
Firstpage
1
Lastpage
2
Abstract
Seven FinFET devices optimized for 7nm technology along with three SRAM cells were evaluated and compared. The high_l device has the lowest OFF current and the highest ON/OFF current ratio. Moreover, 8T SRAM cell achieves the highest SNM which guarantees its robust operation. Hence, 8T SRAM cell using high_l devices is suggested as the choice of memory cell for the discussed 7nm FinFET process.
Keywords
MOSFET; SRAM chips; cache storage; CACTI tool; FinFET device; SPICE; SRAM cell; TCAD tool; cache memory; chip area; circuit-level Verilog-A model; comparative analysis; cross-layer design framework; device mismatch; energy efficient memory design; gate control; on-chip cache; short channel effect; size 7 nm; voltage scaling; Computer architecture; FinFETs; Integrated circuit modeling; Logic gates; Microprocessors; SRAM cells;
fLanguage
English
Publisher
ieee
Conference_Titel
SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2014 IEEE
Conference_Location
Millbrae, CA
Type
conf
DOI
10.1109/S3S.2014.7028219
Filename
7028219
Link To Document