A 0.32V, 55fJ per bit access energy, CMOS 65nm bit-interleaved SRAM with radiation Soft Error tolerance

Author

Clerc, Sylvain ; Abouzeid, Fady ; Gasiot, Gilles ; Gauthier, D. ; Soussan, Dimitri ; Roche, Philippe

Author_Institution

STMicroelectron., Crolles, France

fYear

2012

fDate

May 30 2012-June 1 2012

Firstpage

1

Lastpage

4

Abstract

A 32kb memory is presented with an Ultra Low Voltage optimized 10 transistors bitcell designed to withstand an extended voltage range from 1.2V down to 0.35V, achieving 1.77pJ low energy access. A validation circuit was fabricated in 65nm CMOS and exhibits wafer level yield above 95% at 0.4V, 1MHz. Packaged parts show 0.32V minimum voltage at 490kHz and up to 17X energy gain per operation. The memory terrestrial radiation Soft Error Rate was characterized with no multibit errors reported, enabling future medical appplications radiation reliability through bit-interleaving combined with error correcting code.

Keywords

CMOS integrated circuits; SRAM chips; error correction codes; radiation hardening (electronics); CMOS; bit-interleaved SRAM; bit-interleaving; energy 1.77 pJ; energy 55 fJ; energy gain; error correcting code; frequency 1 MHz; frequency 490 kHz; low energy access; memory terrestrial radiation; radiation soft error tolerance; size 65 nm; soft error rate; transistor bitcell; ultra low voltage; voltage 0.32 V; voltage 0.4 V; voltage 1.2 V to 0.35 V; wafer level yield; Computer architecture; Error correction codes; Logic gates; Measurement; Multiplexing; Random access memory; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

IC Design & Technology (ICICDT), 2012 IEEE International Conference on

Conference_Location

Austin, TX

ISSN

pending

Print_ISBN

978-1-4673-0146-6

Electronic_ISBN

pending

Type

conf

DOI

10.1109/ICICDT.2012.6232860

Filename

6232860