Using ECC and redundancy to minimize vmin induced yield loss in 6T SRAM arrays

VMIN induced Yield Loss is increasing in nanoscale CMOS era, due to quest for performance at low power. SRAM arrays are the largest contributor to this variety of yield loss due to a wide VMIN distribution. To minimize yield loss due to wide SRAM VMIN distribution, authors propose the use of error correction techniques and redundancy. Measured VMIN distribution data of a 30MB SRAM array designed in 32nm process technology node is presented to demonstrate efficacy of redundancy and error correction techniques.