Impacts of work function variation and line-edge roughness on TFET and FinFET devices and logic circuits

Author

Chien-Ju Chen ; Yin-Nien Chen ; Ming-Long Fan ; Hu, V.P.-H. ; Pin Su ; Ching-Te Chuang

Author_Institution

Dept. of Electron. Eng. & Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

2014

fDate

6-9 Oct. 2014

Firstpage

1

Lastpage

2

Abstract

In this paper, we analyze the variability of III-V homojunction tunnel FET (TFET) and FinFET devices and logic circuits operating in near-threshold region. The impacts of work function variation (WFV) and fin line-edge roughness (fin LER) on TFET and FinFET device Ion, Ioff, Cg, two-way NAND delay, switching energy and leakage power are investigated and compared using 3D atomistic TCAD mixed-mode Monte-Carlo simulations. The results indicate that WFV and fin LER have different impacts on I_ON and I_OFF. The delay variability of two-way NAND is aggravated by the Miller capacitance of TFET and FinFET devices.

Keywords

III-V semiconductors; MOSFET; Monte Carlo methods; capacitance; integrated logic circuits; semiconductor device models; technology CAD (electronics); work function; 3D atomistic TCAD mixed-mode Monte-Carlo simulations; III-V homojunction FinFET devices; III-V homojunction tunnel FET; Miller capacitance; TFET devices; leakage power; line-edge roughness; logic circuits; near-threshold region; switching energy; two-way NAND delay; work function variation; Delays; FinFETs; Logic circuits; Monte Carlo methods; Probability distribution; Switches; Three-dimensional displays;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2014 IEEE

Conference_Location

Millbrae, CA

Type

conf

DOI

10.1109/S3S.2014.7028225

Filename

7028225