Impacts of work function variation and line-edge roughness on TFET and FinFET devices and logic circuits

In this paper, we analyze the variability of III-V homojunction tunnel FET (TFET) and FinFET devices and logic circuits operating in near-threshold region. The impacts of work function variation (WFV) and fin line-edge roughness (fin LER) on TFET and FinFET device Ion, Ioff, Cg, two-way NAND delay, switching energy and leakage power are investigated and compared using 3D atomistic TCAD mixed-mode Monte-Carlo simulations. The results indicate that WFV and fin LER have different impacts on I_ON and I_OFF. The delay variability of two-way NAND is aggravated by the Miller capacitance of TFET and FinFET devices.