Microprocessor test and test tool methodology for the 500 MHz IBM S/390 G5 chip

Author

Kusko, Mary P. ; Robbins, Bryan J. ; Snethen, Thomas J. ; Song, Peilin ; Foote, Thomas G. ; Huot, William V.

Author_Institution

IBM Corp., Hopewell Junction, NY, USA

fYear

1998

fDate

18-23 Oct 1998

Firstpage

717

Lastpage

726

Abstract

This paper describes the test tool methodology used for the IBM S/390 microprocessor. An efficient, effective, and automated process providing correct-by-construction test pattern generation, an effective test pattern set, and diagnostics were required. This paper explains the techniques used to accomplish this along with explaining why the method was chosen and how it helped expedite the process

Keywords

CMOS digital integrated circuits; IBM computers; automatic test pattern generation; boundary scan testing; built-in self test; design for testability; fault simulation; integrated circuit testing; microprocessor chips; 500 MHz; BIST; CMOS central processor; DFT; Gatemaker model; IBM S/390 G5 chip; RAM test; TestBench suite; automated process; boundary scan; correct-by-construction test pattern generation; effective test pattern set; fault diagnostics; fault models; integrated EDA test tool; microprocessor test; test tool methodology; Automatic testing; Clocks; Cryptography; Electronic design automation and methodology; Hardware; Logic testing; Microprocessors; Packaging; System testing; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1998. Proceedings., International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-7803-5093-6

Type

conf

DOI

10.1109/TEST.1998.743216

Filename

743216