Title :
FakeFault: a silicon debug software tool for microprocessor embedded memory arrays
Author :
Kwon, Young-Jun ; Mathew, Ben ; Hao, Hong
Author_Institution :
Silicon Graphics Comput. Syst., Mountain View, CA, USA
Abstract :
This paper presents a simple but elegant approach to effectively automate the time-consuming silicon debug procedure for microprocessor embedded memory arrays that allow no direct test modes, based on sequential ATPG with built-in design-for-debug methodology
Keywords :
automatic test pattern generation; automatic test software; boundary scan testing; built-in self test; computer debugging; design for testability; embedded systems; fault simulation; integrated circuit testing; microprocessor chips; software tools; FakeFault; built-in design-for-debug methodology; internal scan; memory dump procedure; microprocessor embedded memory arrays; scan latches location; scan test vectors; sequential ATPG; silicon debug software tool; structured DFT; Automatic test pattern generation; Automatic testing; Clocks; Data mining; Microprocessors; Observability; Pins; Registers; Silicon; Software tools;
Conference_Titel :
Test Conference, 1998. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-5093-6
DOI :
10.1109/TEST.1998.743217
