A2RAM: Low-power 1T-DRAM memory cells compatible with planar and 3D SOI substrates

A novel concept of multi-body 1T-DRAM cell fully compatible with both planar Silicon-On- Insulator substrates and 3D architectures is presented. Its scalability is ensured thanks to the dedicated body partitioning for hole storage and electron current sensing, suppressing the super-coupling effect and allowing the coexistence of electron and hole layers in very thin silicon films. Numerical simulations of the electrostatics and dynamic operation show attractive performance in terms of state discrimination and retention time. These theoretical results on planar devices have been experimentally validated on structures fabricated at CEA-LETI. Finally, we will demonstrate that this body-partitioning concept is extrapolated to 3D tri-gate structures showing high scalability, low-power consumption, long retention time, nondestructive reading, and wide memory window.