Dynamic floating-body instabilities in partially depleted SOI CMOS circuits

Dynamic floating-body instabilities in PD/SOI CMOS devices and circuits are investigated using a physical yet compact MOSFET model in SOISPICE. SOISPICE simulations show how some floating-body effects can be beneficial, but they reveal that the hysteretic nature of the effects causes instabilities. They further exemplify how floating-body charge dynamics can complicate model parameter extraction. Accordingly SOISPICE-aided examinations of SRAM and DRAM circuits imply that conservative designs will be necessitated in PD/SOI technology.<>