Low-energy signal processing using circuit-level timing-error acceptance

In digital signal processing (DSP) applications, large energy gains can be obtained by accepting some degradation in the output signal quality. In this paper, we present static and dynamic techniques for circuit-level timing-error acceptance to significantly improve energy efficiency by shaping the quality-energy tradeoff achievable via aggressive V_DD scaling. The proposed techniques specifically target the earliest and worst timing error offenders to allow for larger V_DD reduction while maintaining high signal quality. We demonstrate the effectiveness of the proposed techniques on image processing applications, including a DCT/IDCT-based image compression system and an image-sharpening filter. The designs were synthesized using a 45nm standard cell library. Results show that 40-60% energy savings can be achieved at less than 1dB loss in the peak signal-to-noise ratio. The overhead for the needed control logic is less than 6% of the area of the original design.