1G DRAM cell with diagonal bit-line (DBL) configuration and edge operation MOS (EOS) FET

Author

Shibahara, K. ; Mori, H. ; Ohnishi, S. ; Oikawa, R. ; Nakajima, K. ; Kojima, Y. ; Yamashita, H. ; Itoh, K. ; Kamiyama, Sachiko ; Watanabe, Hiromi ; Hamada, T. ; Koyama, K.

Author_Institution

ULSI Device Dev. Lab., NEC Corp., Kanagawa, Japan

fYear

1994

fDate

11-14 Dec. 1994

Firstpage

639

Lastpage

642

Abstract

In this paper a new capacitor-over-bit line (COB) cell for 1G DRAM is proposed. The cell area of 0.375 /spl mu/m/sup 2/ was obtained with diagonal bit line (DBL) configuration. An edge operation MOS (EOS) transfer gate has been developed which provides SOI-like small S-factor and V/sub TH/-V/sub SUB/ dependence. A storage capacitance of 28.5 fF was achieved with a Ta/sub 2/O/sub 5/ dielectric film on a hemispherical grain Si (HSG) cylinder structure.<>

Keywords

DRAM chips; MOS memory circuits; capacitance; isolation technology; 1 Gbit; 28.5 fF; DBL configuration; DRAM cell; Si; Ta/sub 2/O/sub 5/; Ta/sub 2/O/sub 5/ dielectric film; capacitor-over-bit line; diagonal bit-line; dynamic RAM; edge operation MOSFET; hemispherical grain Si cylinder structure; storage capacitance; Capacitance; Dielectric films; Earth Observing System; FET integrated circuits; Fabrication; Laboratories; Low voltage; Metalworking machines; National electric code; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1994. IEDM '94. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-2111-1

Type

conf

DOI

10.1109/IEDM.1994.383329

Filename

383329