Title :
Highly manufacturable process technology for reliable 256 Mbit and 1 Gbit DRAMs
Author :
Kang, H.K. ; Kim, K.H. ; Shin, Y.G. ; Park, I.S. ; Ko, K.M. ; Kim, C.G. ; Oh, K.Y. ; Kim, S.E. ; Hong, C.G. ; Kwon, K.W. ; Yoo, J.Y. ; Kim, Y.G. ; Lee, C.G. ; Paick, W.S. ; Suh, D.I. ; Park, C.J. ; Lee, S.I. ; Ahn, S.T. ; Hwang, C.G. ; Lee, M.Y.
Author_Institution :
Semicond. R&D Center, Samsung Electron. Co. Ltd., Kyungki-Do, South Korea
Abstract :
Ta/sub 2/O/sub 5/ dielectric on poly-Si cylinder capacitors, chemical-mechanical polishing (CMP) planarization, pure W bit-line, and Al reflow were integrated into a highly manufacturable DRAM process technology. This technology provided larger process margin, higher reliability, and better design flexibility. In addition, the critical steps of the new process has been reduced by 25% of those of the conventional process. The manufacturability of the technology has been proven by applying it to 16 Mbit density DRAMs with 256 Mbit design rule (0.28 /spl mu/m).<>
Keywords :
CMOS memory circuits; DRAM chips; integrated circuit manufacture; integrated circuit reliability; integrated circuit technology; polishing; 0.28 micron; 1 Gbit; 256 Mbit; Al; Al reflow; CMP planarization; DRAM process technology; Si; Ta/sub 2/O/sub 5/; Ta/sub 2/O/sub 5/ dielectric; W; W bit-line; chemical-mechanical polishing; dynamic RAM; manufacturable process technology; poly-Si cylinder capacitors; reliability; Capacitors; Chemical technology; Dielectrics; Lithography; Manufacturing processes; Planarization; Random access memory; Research and development; Temperature; Tin;
Conference_Titel :
Electron Devices Meeting, 1994. IEDM '94. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-2111-1
DOI :
10.1109/IEDM.1994.383330
