Triple density DRAM cell with Si selective growth channel and NAND-structure

Author

Aoki, M. ; Noguchi, M. ; Hamamoto, T. ; Tokano, K. ; Saito, Y. ; Hoshi, T. ; Watanabe, S.

Author_Institution

Res. & Dev. Center, Toshiba Corp., Kawasaki, Japan

fYear

1994

fDate

11-14 Dec. 1994

Firstpage

631

Lastpage

634

Abstract

We propose a novel trench capacitor cell suitable for shrinkage, named triple density cell (TD-cell). The TD-cell has a planar transistor which overhangs a storage trench capacitor, and Si selective epitaxial growth (SEG) is used for channel formation. The cell size reduces to ultimately 33% for the conventional folded-bit-line arrangement, by combining this stacked configuration and NAND-structured cell arrangement. We also verified and analyzed threshold and sub-threshold transport for transistors made on SEG Si layer.<>

Keywords

DRAM chips; NAND circuits; epitaxial growth; integrated circuit technology; NAND-structure; Si; Si selective growth channel; folded-bit-line arrangement; selective epitaxial growth; stacked configuration; storage trench capacitor; subthreshold transport; threshold transport; trench capacitor cell; triple density DRAM cell; Capacitance; Capacitors; Costs; Electrodes; Epitaxial growth; Fabrication; Random access memory; Research and development; Semiconductor materials; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1994. IEDM '94. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-2111-1

Type

conf

DOI

10.1109/IEDM.1994.383331

Filename

383331