Title :
Efficient gate oxide defect screen for VLSI reliability
Author :
King, J.C. ; Chan, W.Y. ; Chenming Hu
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
We report the feasibility and effectiveness of short voltage stress for oxide defect screen in this paper. Wafer-level in-process voltage stress rather than post-process burn-in may be necessary for defect screening, so that all the thin oxides can be accessed and higher voltage may be used to accelerate the burn-in. Oxide breakdown theory has been successfully used to model this defect control method.<>
Keywords :
CMOS integrated circuits; VLSI; dielectric thin films; electric breakdown; failure analysis; integrated circuit modelling; integrated circuit reliability; integrated circuit testing; integrated circuit yield; production testing; CMOS VLSI; MOS process; VLSI reliability; burn-in acceleration; defect control method; gate oxide defect screen; model; oxide breakdown theory; short voltage stress; thin oxides; wafer-level in-process voltage stress; Breakdown voltage; CMOS process; Circuits; Computer graphics; Electric breakdown; Plasma temperature; Semiconductor device modeling; Silicon; Stress; Very large scale integration;
Conference_Titel :
Electron Devices Meeting, 1994. IEDM '94. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-2111-1
DOI :
10.1109/IEDM.1994.383339
