Partition and global methodologies for IC, Package and Board co-simulation in SiP applications

Author

Wane, Sidina

Author_Institution

NXP-Semicond., Caen

fYear

2007

fDate

8-10 Oct. 2007

Firstpage

451

Lastpage

454

Abstract

This paper presents a global IC-package-board co-simulation methodology for SiP (system-in-package) applications. The proposed methodology, using internal ports (auxiliary sources) concept, is applied to a real-word NXP-Semiconductor SiP test carrier built in Cadence SiP and Optimal SiP-tooling environments. The obtained global simulation results, for identified complete multi-level IC-Package-Board sensitive path, are compared to partition-based approach for frequencies up to 20 GHz. The partition-methodology is validated through careful comparison with measurement, and EM simulations for the analysis of SiP multi-conductor off-chip passive circuitry and on-chip functional components (baluns, harmonic filters). The limits of cascade-based approaches are investigated in reference to a global IC-package-board co-simulation methodology.

Keywords

monolithic integrated circuits; passive networks; system-in-package; Cadence SiP; IC-package-board cosimulation methodology; Optimal SiP-tooling; SiP; internal ports; multiconductor off-chip passive circuitry; on-chip functional components; partition-based approach; real-word NXP-semiconductor test; system-in-package; Application specific integrated circuits; Circuit simulation; Electronic design automation and methodology; Gallium arsenide; Impedance matching; Integrated circuit packaging; Microwave integrated circuits; Radiofrequency integrated circuits; Semiconductor device packaging; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Integrated Circuit Conference, 2007. EuMIC 2007. European

Conference_Location

Munich

Print_ISBN

978-2-87487-002-6

Type

conf

DOI

10.1109/EMICC.2007.4412746

Filename

4412746