W/WNx/poly-Si gate technology for future high speed deep submicron CMOS LSIs

Author

Kasai, K. ; Akasaka, Y. ; Nakajima, Kensuke ; Suehiro, S. ; Suguro, K. ; Oyamatsu, H. ; Kinugawa, M. ; Kakumu, M.

Author_Institution

Semicond. Device Eng. Lab., Toshiba Corp., Kawasaki, Japan

fYear

1994

fDate

11-14 Dec. 1994

Firstpage

497

Lastpage

500

Abstract

In this paper, a new gate structure, W/WNx/poly-Si, was proposed as the breakthrough to combat the serious parasitic effect caused by RC delay of gate electrode in down-scaled CMOS devices. MOSFETs with the gate electrode structure were fabricated with a deep submicron CMOS process. As a result, 1.6/spl Omega//spl square/ gate sheet resistance without an increase in fine line gate was obtained. Moreover, it was demonstrated that the thin WNx layer formed by reactive sputtering can be an excellent barrier layer from the gate oxide integrity and W/poly-Si contact resistivity point of view.<>

Keywords

CMOS integrated circuits; elemental semiconductors; integrated circuit metallisation; large scale integration; silicon; tungsten; tungsten compounds; MOSFETs; W-WN-Si; W/WNx/poly-Si gate technology; W/poly-Si contact resistivity; barrier layer; deep submicron CMOS LSI; downscaled CMOS devices; gate electrode RC delay; gate electrode structure; gate oxide integrity; high speed CMOS LSI; reactive sputtering; CMOS technology; Degradation; Delay; Electrodes; Laboratories; Large scale integration; Research and development; Semiconductor devices; Silicides; Sputtering;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1994. IEDM '94. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-2111-1

Type

conf

DOI

10.1109/IEDM.1994.383360

Filename

383360