DocumentCode
2526610
Title
Boundary scan BIST methodology for reconfigurable systems
Author
Su, Chauchin ; Jeng, Shung-Won ; Chen, Yue-Tsang
Author_Institution
Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
fYear
1998
fDate
18-23 Oct 1998
Firstpage
774
Lastpage
783
Abstract
The interconnect BIST is achieved by the on-line polling for the composite vectors that contain the encoded information, for the test generation and response evaluation on selective drivers and receivers to adapt to the changing configuration
Keywords
boundary scan testing; built-in self test; integrated circuit interconnections; integrated circuit testing; reconfigurable architectures; boundary scan BIST methodology; composite vectors; encoded information; interconnect BIST; on-line polling; reconfigurable systems; response evaluation; test generation; Automatic testing; Backplanes; Built-in self-test; Circuit testing; Driver circuits; Impedance; Integrated circuit interconnections; Logic testing; Switches; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1998. Proceedings., International
Conference_Location
Washington, DC
ISSN
1089-3539
Print_ISBN
0-7803-5093-6
Type
conf
DOI
10.1109/TEST.1998.743260
Filename
743260
Link To Document