Electrothermal behavior of deep submicron nMOS transistors under high current snapback (ESD/EOS) conditions

Author

Amerasekera, A. ; Seitchik, J.A.

Author_Institution

Semicond. Process & Device Center, Texas Instrum. Inc., Dallas, TX, USA

fYear

1994

fDate

11-14 Dec. 1994

Firstpage

455

Lastpage

458

Abstract

We present the underlying mechanisms of second breakdown in deep submicron nMOS transistors under high current snapback conditions. The onset of second breakdown is shown to be determined by a rapid increase in the thermally generated component of the substrate (base) current. Simplified simulation methodologies for evaluating high current robustness using isothermal device simulations are demonstrated and good correlations with experimental data have been obtained.<>

Keywords

MOSFET; electric breakdown; electrostatic discharge; semiconductor device models; simulation; thermal analysis; EOS; ESD; NMOS transistors; deep submicron NMOSFET; electrothermal behavior; high current robustness; high current snapback conditions; isothermal device simulations; n-channel MOSFET; second breakdown; simulation methodologies; substrate current; Earth Observing System; Electric breakdown; Electrostatic discharge; Electrothermal effects; Isothermal processes; MOS devices; MOSFETs; Process design; Robustness; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1994. IEDM '94. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-2111-1

Type

conf

DOI

10.1109/IEDM.1994.383370

Filename

383370