Josephson-CMOS integrated circuits

Author

Ghoshal, U. ; Hebert, D. ; Van Duzer, T.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

fYear

1994

fDate

11-14 Dec. 1994

Firstpage

445

Lastpage

448

Abstract

We report the development of the first-ever monolithically integrated Josephson-CMOS circuits for digital memory, detector, and magnetometry applications at 4 K. The technology combines a 1.2 /spl mu/m dual-poly, n-well CMOS process, and a Nb/AlO/sub x/Nb trilayer process yielding Josephson junctions with critical current densities of 0.4-0.8 kA/cm/sup 2/. We discuss the nonhysteretic, low-voltage (1 V) operation of CMOS devices at 4 K, and the gigahertz operation of the Josephson-CMOS interface circuits and bit-line current-sensing circuits of a Josephson-CMOS RAM.<>

Keywords

CMOS memory circuits; Josephson effect; aluminium compounds; critical current density (superconductivity); integrated circuit technology; niobium; random-access storage; superconducting memory circuits; 1 V; 1.2 micron; 4 K; Josephson junctions; Josephson-CMOS RAM; Josephson-CMOS integrated circuits; Nb-AlO-Nb; Nb/AlO/sub x/Nb trilayer process; Si; bit-line current-sensing circuits; critical current densities; detector applications; digital memory; dual-poly n-well CMOS process; gigahertz operation; interface circuits; magnetometry applications; monolithically integrated circuits; nonhysteretic LV operation; CMOS process; CMOS technology; Critical current density; Detectors; Integrated circuit technology; Integrated circuit yield; Josephson junctions; Magnetic circuits; Niobium; Read-write memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1994. IEDM '94. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-2111-1

Type

conf

DOI

10.1109/IEDM.1994.383372

Filename

383372