• DocumentCode
    2526866
  • Title

    A highly testable and diagnosable fabrication process test chip

  • Author

    Bhavsar, Dilip K. ; Echeruo, Ugonna ; Akeson, David R. ; Bowhill, William J.

  • Author_Institution
    Alpha Technol. Group, Compaq Comput. Corp., Shrewsbury, MA, USA
  • fYear
    1998
  • fDate
    18-23 Oct 1998
  • Firstpage
    853
  • Lastpage
    861
  • Abstract
    We present the concept and prototype of the Logic Test Vehicle (LTV), a novel tool for ramp-up, qualification and monitoring of semiconductor fabrication processes. The LTV overcomes some of the known shortcomings of SRAM test vehicles used today for these purposes. It employs test circuitry which is more complex and more representative of the complexities found on real products yet retains testability and diagnosability, the two most important attributes required of test vehicles
  • Keywords
    SRAM chips; automatic testing; integrated circuit testing; logic testing; SRAM test vehicles; diagnosable fabrication process; logic test vehicle; monitoring; qualification; ramp-up; semiconductor fabrication processes; test circuitry; testable fabrication process; Circuit testing; Fabrication; Geometry; Libraries; Life testing; Logic arrays; Logic testing; Qualifications; Random access memory; Vehicles;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 1998. Proceedings., International
  • Conference_Location
    Washington, DC
  • ISSN
    1089-3539
  • Print_ISBN
    0-7803-5093-6
  • Type

    conf

  • DOI
    10.1109/TEST.1998.743274
  • Filename
    743274