Cache RAM inductive fault analysis with fab defect modeling

Author

Mak, TM ; Bhattacharya, Debika ; Prunty, Cheryl ; Roeder, Bob ; Ramadan, Nermine ; Ferguson, Joel ; Yu, Jianlin

Author_Institution

Intel Corp., Santa Clara, CA, USA

fYear

1998

fDate

18-23 Oct 1998

Firstpage

862

Lastpage

871

Abstract

This paper describes how an inductive fault analysis (IFA) method was used in determining the expected yield and test algorithm effectiveness in SRAMs. One portion of the paper describes the process of gathering and correlating defect data from different sources to get a meaningful and accurate defect distribution. This data is used in the IFA software to weight the probability of faults occurring. With the fault data from two SRAM cells the yield of those devices is estimated and compared with actual yield. The effectiveness of certain test patterns is also evaluated based on the probable faults for those circuits

Keywords

SRAM chips; automatic testing; cache storage; fault diagnosis; integrated circuit testing; integrated circuit yield; production testing; SRAMs; cache RAM; defect distribution; expected yield; fab defect modeling; inductive fault analysis; probability; test algorithm effectiveness; test patterns; Algorithm design and analysis; Bridge circuits; Circuit faults; Circuit simulation; Circuit testing; Educational institutions; Fabrication; Manufacturing processes; Random access memory; Read-write memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1998. Proceedings., International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-7803-5093-6

Type

conf

DOI

10.1109/TEST.1998.743275

Filename

743275