Optimized complementary 40 V power LDMOS-FETs use existing fabrication steps in submicron CMOS technology

Author

Efland, T. ; Keller, T. ; Keller, S. ; Rodriguez, J.

Author_Institution

Texas Instrum. Inc., Dallas, TX, USA

fYear

1994

fDate

11-14 Dec. 1994

Firstpage

399

Lastpage

402

Abstract

This paper discusses development of state-of-the-art complementary isolated lateral 40 V rated power MOSFETs. The goals of this project were to provide BV specific devices for use with an existing merged VLSI technology. Devices meeting this goal were fabricated in a production manufacturing environment with no extra cost added to the process. The p-channel FET has a BV=60 V, and R/sub s/p=2.71 m/spl Omega/ cm/sup 2/ @V/sub gs/=15 V, and for the n-channel FET, BV=47 V and R/sub sp/=0.67 m/spl Omega/cm/sup 2/ @V/sub gs/=15 V. These devices are seen to be very competitive solutions with advanced integral on-chip intelligence.<>

Keywords

CMOS integrated circuits; VLSI; integrated circuit manufacture; integrated circuit technology; power MOSFET; power integrated circuits; 40 V; BV specific devices; complementary isolated lateral MOSFETs; fabrication steps; integral on-chip intelligence; merged VLSI technology; p-channel FET; power LDMOS-FETs; production manufacturing environment; submicron CMOS technology; CMOS technology; Competitive intelligence; Costs; FETs; Fabrication; Isolation technology; Low voltage; Manufacturing processes; Power integrated circuits; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1994. IEDM '94. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-2111-1

Type

conf

DOI

10.1109/IEDM.1994.383383

Filename

383383