Detecting resistive shorts for CMOS domino circuits

Author

Chang, Jonathan T Y ; McCluskey, Edward J.

Author_Institution

Center for Reliable Comput., Stanford Univ., CA, USA

fYear

1998

fDate

18-23 Oct 1998

Firstpage

890

Lastpage

899

Abstract

We investigate defects in CMOS domino gates and derive the test conditions for them. Very-Low-Voltage Testing can improve the defect coverage, which we define as the maximum detectable resistance, of intra-gate and inter-gate resistive shorts. We also propose a new keeper design for CMOS domino circuits. The new keeper design has low performance impact and is best for small CMOS domino gates. Keepers can eliminate the floating nodes in CMOS domino logic gates

Keywords

CMOS logic circuits; fault diagnosis; integrated circuit testing; logic gates; logic testing; CMOS domino circuits; defect coverage; domino gates; floating nodes; inter-gate resistive shorts; intra-gate resistive shorts; keeper design; maximum detectable resistance; very-low-voltage testing; CMOS logic circuits; Circuit faults; Circuit noise; Circuit testing; Clocks; Delay; Logic gates; Low voltage; Temperature; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1998. Proceedings., International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-7803-5093-6

Type

conf

DOI

10.1109/TEST.1998.743280

Filename

743280

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2526972