Title :
Compact two-pattern test set generation for combinational and full scan circuits
Author :
Hamzaoglu, Ilker ; Patel, Janak H.
Author_Institution :
Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
Abstract :
This paper presents two algorithms for generating compact test sets for combinational and full scan circuits under the transition and CMOS stuck-open fault models; Redundant Vector Elimination (RVE) and Essential Fault Reduction (EFR). These algorithms together with the dynamic compaction algorithm are incorporated into an advanced ATPG system for combinational circuits, called MinTest. The test sets generated by MinTest are 30% smaller than the previously published two-pattern test set compaction results for the ISCAS85 and full scan version of the ISCAS89 benchmark circuits
Keywords :
CMOS logic circuits; VLSI; automatic test pattern generation; combinational circuits; fault simulation; integrated circuit testing; logic testing; redundancy; CMOS stuck-open fault models; ISCAS85 benchmark circuits; ISCAS89 benchmark circuits; MinTest; advanced ATPG system; combinational circuits; dynamic compaction algorithm; essential fault reduction; full scan circuits; redundant vector elimination; transition fault models; two-pattern test set generation; Automatic test pattern generation; Benchmark testing; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Compaction; Fault detection; Semiconductor device modeling; Very large scale integration;
Conference_Titel :
Test Conference, 1998. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-5093-6
DOI :
10.1109/TEST.1998.743288
