2527168

Code Generation Schema For Modulo Scheduled Loops

Rau, B. Ramakrishna ; Schlansker, Michael S. ; Tirumalai, P.P.

Hewlett Packard Laboratories

1992

1-4 Dec 1992

158

169

Delay; Hardware; Motion control; Pipeline processing; Processor scheduling; Reduced instruction set computing; Registers; Scheduling algorithm; Software algorithms; VLIW;

English

ieee

Microarchitecture, 1992. MICRO 25., Proceedings of the 25th Annual International Symposium on

0-8186-3175-9

conf

10.1109/MICRO.1992.697012

697012