Impact of boron diffusion through O/sub 2/ and N/sub 2/O gate dielectrics on the process margin of dual-poly low power CMOS

Author

Krisch, K.S. ; Manchanda, L. ; Baumann, F.H. ; Green, M.L. ; Brasen, D. ; Feldman, L.C. ; Ourmazd, A.

Author_Institution

AT&T Bell Labs., Murray Hill, NJ, USA

fYear

1994

fDate

11-14 Dec. 1994

Firstpage

325

Lastpage

328

Abstract

This work evaluates the impact of boron penetration from p/sup +/-polysilicon on process margin and system performance. We experimentally demonstrate that small (3/spl sigma/=/spl plusmn/3 /spl Aring/) variations in gate oxide thickness, coupled with boron penetration, can increase the spread in threshold voltages by /spl plusmn/100 mV or more. By inhibiting boron penetration, N/sub 2/O grown oxides are shown to improve V/sub T/ control, thereby enhancing the process margin. We present a physically-based model to describe boron penetration as a function of t/sub ox/, and analyze the impact of increased V/sub T/ variation on subthreshold leakage current and on the resultant off-state power consumption.<>

Keywords

CMOS integrated circuits; boron; dielectric thin films; diffusion; ion implantation; semiconductor process modelling; B diffusion; B penetration; N/sub 2/O; N/sub 2/O ambient; N/sub 2/O grown oxides; O/sub 2/; O/sub 2/ ambient; O/sub 2/ grown oxides; Si; dual-poly low power CMOS; gate dielectrics; gate oxide thickness; offstate power consumption; p/sup +/-polysilicon; physically-based model; process margin; subthreshold leakage current; threshold voltages; Aluminum; Annealing; Boron; Capacitance measurement; Capacitance-voltage characteristics; Dielectrics; Position measurement; Q measurement; Thickness measurement; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1994. IEDM '94. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-2111-1

Type

conf

DOI

10.1109/IEDM.1994.383402

Filename

383402