DocumentCode :
252735
Title :
Power noise isolation in a silicon interposer with through silicon vias
Author :
Myunghoi Kim ; Dong-Hwan Shin ; Man-Seok Um ; In-Bok Yom
Author_Institution :
Satellite & Wireless RF Technol. Res. Sect., ETRI, Daejeon, South Korea
fYear :
2014
fDate :
3-5 Dec. 2014
Firstpage :
805
Lastpage :
808
Abstract :
In this paper, we present a new structure of a power distribution network (PDN) in silicon interposers with through silicon vias (TSVs) to suppress the high-frequency power/ground noise including simultaneous switching noise. The proposed PDN structure employs the resonant structure consisting of metal patterns and TSVs. To examine the effect of design parameters of the resonant structure on noise suppression characteristics, we present Bloch analysis based on a phase of Bloch impedance and Floquet´s theorem. Simulation results show a good correlation between Bloch analysis and a full-wave simulation. Power noise isolation of the proposed PDN structure is verified using full-wave simulations.
Keywords :
elemental semiconductors; integrated circuit modelling; integrated circuit noise; interference suppression; silicon; three-dimensional integrated circuits; Bloch analysis; Bloch impedance; Floquet theorem; Si; full-wave simulations; high-frequency power-ground noise; noise suppression characteristics; power distribution network; power noise isolation; silicon interposer; switching noise; through silicon vias; Analytical models; Impedance; Metals; Noise; Packaging; Silicon; Through-silicon vias;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Packaging Technology Conference (EPTC), 2014 IEEE 16th
Conference_Location :
Singapore
Type :
conf
DOI :
10.1109/EPTC.2014.7028315
Filename :
7028315
Link To Document :
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