Characterization and model of the hot-carrier-induced offset voltage of analog CMOS differential stages

Using a specifically developed measurement setup and a test structure typical for analog applications, high precision measurements of the stress-induced offset voltage degradation of differential pairs are realized. A model is developed that traces back the hot-carrier-induced offset voltage to a single transistor parameter thus simplifying greatly statements about analog circuit reliability. Extrapolation to operating conditions yields valuable information for analog design in the sub-/spl mu/m CMOS regime.<>