Characterization and model of the hot-carrier-induced offset voltage of analog CMOS differential stages

Author

Thewes, R. ; Goser, K. ; Weber, W.

Author_Institution

Corp. Res. & Dev., Siemens AG, Munich, Germany

fYear

1994

fDate

11-14 Dec. 1994

Firstpage

303

Lastpage

306

Abstract

Using a specifically developed measurement setup and a test structure typical for analog applications, high precision measurements of the stress-induced offset voltage degradation of differential pairs are realized. A model is developed that traces back the hot-carrier-induced offset voltage to a single transistor parameter thus simplifying greatly statements about analog circuit reliability. Extrapolation to operating conditions yields valuable information for analog design in the sub-/spl mu/m CMOS regime.<>

Keywords

CMOS analogue integrated circuits; differential amplifiers; hot carriers; integrated circuit measurement; integrated circuit modelling; integrated circuit reliability; analog CMOS differential stages; analog circuit reliability; characterization; differential pairs; hot-carrier-induced offset voltage; measurement setup; model; offset voltage degradation; test structure; transistor parameter; Analog circuits; Circuit testing; Current measurement; Degradation; Differential amplifiers; Hot carriers; Operational amplifiers; Semiconductor device modeling; Stress measurement; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1994. IEDM '94. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-2111-1

Type

conf

DOI

10.1109/IEDM.1994.383407

Filename

383407