An almost full-scan BIST solution-higher fault coverage and shorter test application time

This paper illustrates that for existing scan-based Built-In Self-Test (BIST) architectures under the pseudo-random testing scheme, scanning all flip-flops may not be the best strategy for achieving high fault coverage with a practical limit on test length. In general, for scan-based BIST, not scanning flip-flops with relatively high pseudo-random observabilities through the primary outputs may indeed improve the fault coverage as well as the test application time. We illustrate the issues and present a flip-flop selection strategy for scan-based BIST to maximize the fault coverage and reduce the test application time. Experiments have been conducted based on an industrial tool psb2 for several benchmark circuits. The results show that the almost-full-scan circuits based on our flip-flop selection strategy can achieve higher fault coverages and significantly shorter test application time as compared with the full-scan circuits