Title :
Probabilistic mixed-model fault diagnosis
Author :
Lavo, David B. ; Chess, Brian ; Larrabee, Tracy ; Hartanto, Ismed
Author_Institution :
California Univ., Santa Cruz, CA, USA
Abstract :
Previously-proposed strategies for VLSI fault diagnosis have suffered from a variety of self-imposed limitations. Some techniques are limited to a specific fault model, and many will fail in the face of any unmodeled behavior or unexpected data. Others apply ad-hoc or arbitrary scoring mechanisms to fault candidates, making the results difficult to interpret or to compare with the results from other algorithms. This paper outlines an approach to fault diagnosis that is robust, comprehensive, extendable, and practical. By introducing a probabilistic framework for diagnostic prediction, it is designed to incorporate disparate diagnostic algorithms, different sets of data, and a mixture of fault models into a single diagnostic result. Results from diagnosis experiments on a Hewlett-Packard ASIC and FIB inserted defects are presented
Keywords :
Bayes methods; VLSI; application specific integrated circuits; automatic test pattern generation; fault simulation; integrated circuit testing; logic testing; probabilistic logic; ASIC; Bayes decision theory; FIB inserted defects; VLSI fault diagnosis; bridging fault diagnosis; diagnostic prediction; different sets of data; disparate diagnostic algorithms; fault signatures; mixture of fault models; probabilistic framework; probabilistic mixed-model fault diagnosis; robust approach; single diagnostic; stuck-at scoring; Algorithm design and analysis; Application specific integrated circuits; Circuit faults; Failure analysis; Fault diagnosis; Information resources; Predictive models; Process design; Robustness; Very large scale integration;
Conference_Titel :
Test Conference, 1998. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-5093-6
DOI :
10.1109/TEST.1998.743308