Failure mechanisms of flash cell in program/erase cycling

The impact of program/erase cycling on flash memory cell is reviewed considering both performance degradation of the typical bit and the evolution of the erase threshold voltage distribution of the whole memory array. Emphasis is given to the failure mechanisms which affect flash memory endurance: the erratic erase phenomenon is discussed with reference to the model recently reported in the literature and a new degradation mechanism, induced by parasitic drain stress conditions in program/erase cycling, is presented.<>