Title :
Mixed-voltage interface ESD protection circuits for advanced microprocessors in shallow trench and LOCOS isolation CMOS technologies
Author :
Voldman, S.H. ; Gerosa, G.
Author_Institution :
Microelectron. Div., IBM Corp., Essex Junction, VT, USA
Abstract :
Optimization of a 3.3-V/ 5.0-V tolerant electrostatic discharge (ESD) protection network for both diffused n-well/LOCOS and retrograde well/shallow trench isolation (STI) CMOS technologies in a RISC microprocessor is discussed. ESD-related semiconductor-process key design features, ESD circuit operation, data, simulation and failure analysis are presented. ESD robustness of 4000-V human body model (HBM), 400-V machine model (MM), and 1500-V charge device model (CDM) is achieved in both technologies using a common design.<>
Keywords :
CMOS digital integrated circuits; electrostatic discharge; failure analysis; integrated circuit layout; integrated circuit reliability; isolation technology; microprocessor chips; protection; reduced instruction set computing; 3.3 V; 5 V; ESD protection circuits; LOCOS isolation; RISC microprocessor; advanced microprocessors; diffused n-well/LOCOS type; electrostatic discharge protection; failure analysis; isolation CMOS technologies; mixed-voltage interface; retrograde well/STI type; shallow trench isolation; simulation; Analytical models; Biological system modeling; CMOS technology; Circuits; Electrostatic discharge; Isolation technology; Microprocessors; Protection; Reduced instruction set computing; Semiconductor device modeling;
Conference_Titel :
Electron Devices Meeting, 1994. IEDM '94. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-2111-1
DOI :
10.1109/IEDM.1994.383413
