Title :
A novel architecture to reduce test time in march-based SRAM tests
Author :
Voyiatzis, I. ; Efstathiou, C. ; Tsiatouhas, Y. ; Sgouropoulou, C.
Abstract :
We present a scheme to reduce the test application time in memory march algorithm application by providing the capability to enable in parallel more than one output of the address decoder during write operations. The reduction in test time, depending on the march algorithm, ranges from 25% to 60%, while the hardware overhead increase for 1 Kbyte SRAM´s is less than 2,5%.
Keywords :
SRAM chips; integrated circuit testing; address decoder; march-based SRAM test; memory march algorithm; memory size 1 KByte; test application time reduction; test time reduction; write operation; Algorithm design and analysis; Computer architecture; Decoding; Microprocessors; Nanoscale devices; Random access memory; Testing;
Conference_Titel :
Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2012 7th International Conference on
Conference_Location :
Gammarth
Print_ISBN :
978-1-4673-1926-3
DOI :
10.1109/DTIS.2012.6232963
