• DocumentCode
    2527539
  • Title

    Improved performance irregular quasi-cyclic LDPC code design from BIBD’s using threshold minimization

  • Author

    Patil, Siddarama R. ; Pathak, Sant S.

  • Author_Institution
    Dept. of Electr. & Electron. Commun. Eng., Indian Inst. of Technol., Kharagpur
  • fYear
    2008
  • fDate
    19-21 Nov. 2008
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    In this paper we propose a novel method for designing irregular quasi-cyclic low-density parity-check (LDPC) codes from Balanced Incomplete Block Designs (BIBDpsilas). The design method hinges around finding the optimum degree profile by minimizing the threshold using density evolution. The approach for designing short block length codes is robust for practical implementation and has been found to exhibit considerable performance gain that may be attributed to a good degree profile for the codes. The design takes into consideration the code rate and code length as variable parameters. The simulation results for the designed codes are compared with regular and irregular quasi-cyclic BIBD based LDPC codes and found a relatively higher performance in terms of BER.
  • Keywords
    block codes; minimisation; parity check codes; balanced incomplete block design; density evolution; irregular quasi cyclic LDPC code design; short block length code; threshold minimization; Bit error rate; Design engineering; Design methodology; Equations; Fasteners; Minimization methods; Parity check codes; Performance gain; Robustness; Sparse matrices;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    TENCON 2008 - 2008 IEEE Region 10 Conference
  • Conference_Location
    Hyderabad
  • Print_ISBN
    978-1-4244-2408-5
  • Electronic_ISBN
    978-1-4244-2409-2
  • Type

    conf

  • DOI
    10.1109/TENCON.2008.4766569
  • Filename
    4766569