A high performance 0.35 /spl mu/m logic technology for 3.3 V and 2.5 V operation

Author

Bohr, M. ; Ahmed, S.U. ; Brigham, L. ; Chau, R. ; Gasser, R. ; Green, R. ; Hargrove, W. ; Lee, E. ; Natter, R. ; Thompson, S. ; Weldon, K. ; Yang, S.

Author_Institution

Portland Technol. Dev., Intel Corp., Hillsboro, OR, USA

fYear

1994

fDate

11-14 Dec. 1994

Firstpage

273

Lastpage

276

Abstract

A 0.35 /spl mu/m logic technology has been developed with high performance transistors and four layers of planarized interconnect. A 3.3 V BiCMOS version is used for compatibility with 3.3 V and 5.0 V I/Os. A 2.5 V CMOS version is used for increased performance, lower power and lower cost. 3.3 V CMOS devices have channel lengths of <0.25 /spl mu/m and 2.5 V devices have channel lengths of <0.20 /spl mu/m. Using a CV/I performance metric, these are the fastest devices reported to date using 0.35 /spl mu/m lithography. 1 Mbit SRAMs have been built using this technology with a 20.5 /spl mu/m/sup 2/ 6 T cell size.<>

Keywords

BiCMOS digital integrated circuits; BiCMOS logic circuits; CMOS logic circuits; integrated circuit interconnections; integrated circuit metallisation; 0.35 micron; 2.5 V; 3.3 V; BiCMOS version; CMOS version; SRAMs; four layered planarized interconnect; high performance transistors; logic IC; logic technology; subhalf micron lithography; CMOS technology; Costs; Energy consumption; Integrated circuit interconnections; Isolation technology; Lithography; Logic devices; Measurement; Transistors; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1994. IEDM '94. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-2111-1

Type

conf

DOI

10.1109/IEDM.1994.383414

Filename

383414