Improving IO test and system evaluation via data sharing

High speed I/O circuits are becoming increasingly critical as technology scales to increase system bandwidth and decrease power dissipation, die area and system cost. Highly integrated SOCs are currently equipped with large numbers of serial links to enable processing of high bandwidth data streams. There are two major challenges to continued scaling of highspeed I/Os: band-limited channels and timing uncertainty that require a good knowledge on customer system usage. In addition the increase push for customer differentiation and OEM´s pushing more designs to low cost and less skilled design teams adds to the challenge. Adequate learning data sharing between customers and silicon provider is key in these emerging markets to meet quality and Time to Market targets.