Closed-form expressions for extraction of capacitances in multilayer VLSI interconnects

In this work, we report closed-form analytical expressions for capacitances in multilayer VLSI interconnect circuits, using conventional techniques for analysis of strip-line like structures. Variational analysis combined with transverse transmission line technique is used for the determination of capacitances, and a new set of closed-form expressions are derived which gives accurate results without any inherent assumptions. The comparisons of the results with available data in the published literature, as well as 3-D simulation results, are also discussed.