DocumentCode
2527607
Title
Architecture and HW/SW validation of nonlinear Border-Preserving Interpolator
Author
Boudabous, Anis ; Ben Atitallah, Ahmed ; Khriji, Lazhar ; Masmoudi, Nouri
Author_Institution
Nat. Sch. of Eng., Univ. of Sfax, Sfax, Tunisia
fYear
2012
fDate
16-18 May 2012
Firstpage
1
Lastpage
4
Abstract
In this paper, a new hardware implementation of the Border-Preserving Interpolator is presented. The object of this proposed work is to achieve significant run time performance using a hardware development board. It also demonstrates consistent image quality performance among a variety of images. This validation show that our implementation based on HW/SW design speeds up the interpolation process as well as preserving a high image quality.
Keywords
edge detection; hardware-software codesign; HW/SW design; HW/SW validation; hardware development board; hardware implementation; image quality performance; nonlinear border-preserving interpolator; run time performance; Computer architecture; Educational institutions; Field programmable gate arrays; Hardware; Interpolation; Optical filters; Software; FPGA; HW/SW; Nonlinear interpolation; Reconfigurable Architecture; color image;
fLanguage
English
Publisher
ieee
Conference_Titel
Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2012 7th International Conference on
Conference_Location
Gammarth
Print_ISBN
978-1-4673-1926-3
Type
conf
DOI
10.1109/DTIS.2012.6232968
Filename
6232968
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