Thermal effects of TSV (through silicon via) with void

Author

Yunna Sun ; Hui-Yeol Kim ; Yan Wang ; Guifu Ding ; Junhong Zhao ; Hong Wang

Author_Institution

Sch. of Electron. Inf. & Electr. Eng., Shanghai Jiaotong Univ., Shanghai, China

fYear

2014

fDate

3-5 Dec. 2014

Firstpage

307

Lastpage

312

Abstract

Duo to the TSV fabrication process, the void or stream often exists in the TSV. As we all know the void and stream cannot easily being avoided, the thermal mechanical reliability of TSV integrated circuit (IC) shall be studied deeply for evaluating the fatigue life of the IC products and rearranging the location of TSVs to relieving thermal issues. In addition, the thermal mechanism of void model is different from the vertical TSV. Therefore, it is meaningful and significant to study the thermal stability of void model. This paper evaluates the thermal mechanical stability during the change of the void location and size by finite element method (FEM). The interfacial lines of void TSV suffer different thermal stress and strain induced by the unbalanced deformation of the void, and the interaction of void and TSV.

Keywords

deformation; fatigue; finite element analysis; integrated circuit packaging; integrated circuit reliability; mechanical stability; stress-strain relations; thermal stability; three-dimensional integrated circuits; voids (solid); TSV integrated circuit; fatigue life; finite element method; thermal mechanical reliability; thermal mechanical stability; thermal strain; thermal stress; through silicon vias; void deformation; void interfacial lines; void location; void model; void size; void-TSV interaction; Integrated circuit modeling; Stability analysis; Stress; Thermal stability; Thermal stresses; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics Packaging Technology Conference (EPTC), 2014 IEEE 16th

Conference_Location

Singapore

Type

conf

DOI

10.1109/EPTC.2014.7028335

Filename

7028335